What Is IIT Kharagpur Applied VLSI Design?
Key Highlights: IIT Kharagpur Applied VLSI Design
Why Choose the IIT Kharagpur VLSI Course?
Chip design involves several connected stages. Engineers must understand the system architecture, write RTL, verify functionality, design analog components where required, and prepare the physical layout for sign-off.
The IIT Kharagpur Applied VLSI Design programme includes:
Connected chip-design curriculum: Starts from the basic semiconductor concepts and goes up to the stages related to design and verification of analog circuits, the layout and finally, the silicon validation.
Early verification milestone: This phase introduces the concept of testbenches, SystemVerilog assertions, and UVM, with the goal of achieving coverage closure within the first 11 weeks of learning.
Analog and mixed-signal design: Teaches how to design amplifier circuits, sensor interface circuits, comparator circuits, custom layout, and even analog/mixed-signal validation techniques.
Physical design and sign-off: Teaches how to design amplifier circuits, sensor interface circuits, comparator circuits, custom layout, and even analog/mixed-signal validation techniques.
Experience working with tools: You will be given hands-on tool exposure through open-source RTL to GDSII flow and learning commercial analog design tools.
Awareness of AI-assisted EDA: You will get an understanding of the potential use of AI-assisted tools in verification, debugging, placement, and timing optimization, respectively.
Capstone project: In this project, you will be developing a chipdesigning project from the architectural stage to RTL design, verification, analog integration, and finally the physical sign-off.
What Will You Learn in the IIT Kharagpur Applied VLSI Design Syllabus?
The IIT Kharagpur Applied VLSI Design Syllabus includes a bridge that lasts for two weeks at the beginning of the course. The program spans over 30 weeks and consists of six modules and a capstone project.
The program consists of these modules:
Bridge: Semiconductor Readiness Bootcamp
Weeks -2 to 0 | Pre-course preparation
Topics Covered:
Track A for software and embedded backgrounds: Mathematics for VLSI, digital electronics, semiconductor basics, logic design, and finite state machines.
Track B for ECE and hardware backgrounds: Python, C programming, Linux, and Git.
Digital controller implementation as the Bridge deliverable.
Skills Acquired:
Revising relevant hardware or programming fundamentals
Identifying and addressing knowledge gaps
Preparing for the main chip-design curriculum
Implementing a digital controller
Module 1: Semiconductor Foundations and Chip Architecture
Weeks 1–3
Topics Covered:
Semiconductor industry, fabless companies, foundries, OSAT, and packaging
India's Semiconductor Mission and the AI chip market
CMOS, MOSFETs, process technology, scaling, and FinFET
Functional specifications, system architecture, and block diagrams
CPU fundamentals, memory hierarchy, and cache
AXI/APB interfaces, RISC-V architecture, and power-area budgets
First RTL-to-GDSII flow using OpenLane
Skills Acquired:
Understanding the semiconductor value chain
Analysing basic device behaviour and process scaling
Designing a system architecture for a small SoC
Making memory, bus, power, and area decisions
Reading the output of a complete open-source design flow
Module 2: Digital Design and RTL Engineering
Weeks 4–7
Topics Covered:
Verilog and SystemVerilog coding styles
Combinational and sequential logic
Finite state machine coding
Datapath, control logic, and pipelining
Clock gating, reset architecture, and low-power RTL
RISC-V peripheral integration and AXI/APB interfacing
FPGA prototyping, linting, structural checks, and synthesis
Skills Acquired:
Writing synthesizable SystemVerilog
Building digital logic and state machines
Understanding throughput and low-power design trade-offs
Integrating a RISC-V peripheral subsystem
Checking RTL before synthesis
Preparing a clean RTL handoff
Module 3: Verification and Quality Engineering
Weeks 8–11
Topics Covered:
Verification planning and coverage models
Directed and constrained-random stimulus
Self-checking testbenches and scoreboards
SystemVerilog assertions and functional coverage
Python-based regression automation
UVM architecture, agents, sequences, drivers, monitors, and scoreboards
Register abstraction layer basics
Formal verification, clock-domain crossing, and gate-level simulation
AI-assisted debugging and regression analysis
Skills Acquired:
Preparing verification plans
Building a UVM verification environment
Writing SystemVerilog assertions
Closing functional coverage to an agreed threshold
Automating regression tests and analysing reports
Identifying failures and debugging designs
Week 11 checkpoint: The programme identifies this point as a core verification-capability milestone.
Module 4: Analog and Mixed-Signal Design
Weeks 12–17
Topics Covered:
Differential amplifiers, current mirrors, comparators, and biasing
Mismatch, offset, common-mode rejection, and supply rejection
Amplifier design, frequency compensation, and stability
Corner and Monte Carlo simulation
Sensor interfacing and ultra-low-power design
ADC/DAC architectures, sample-and-hold circuits, and PLLs
Custom layout, matching, shielding, and parasitic extraction
Analog-mixed-signal verification and co-simulation
Skills Acquired:
Designing and simulating an amplifier or analog front-end
Developing a comparator against specified requirements
Understanding sensor interfaces and low-power circuits
Analysing circuit behaviour across PVT corners
Creating matching-aware layouts
Checking the interaction between analog and digital blocks
Module 5: Physical Design, Sign-off and Tape-out Readiness
Weeks 18–23
Topics Covered:
RTL-to-gate synthesis and timing constraints
Scan insertion and ATPG coverage
Analog macro integration
Floorplanning, pad-ring planning, and power grids
Placement and congestion analysis
Clock-tree synthesis and routing
Static timing analysis and multi-corner timing closure
Electromigration, IR-drop, and reliability analysis
DRC, LVS, antenna checks, and physical sign-off
AI-assisted placement and timing optimisation
Skills Acquired:
Understanding the physical implementation flow
Planning mixed-signal chip layouts
Analysing congestion and clock-tree requirements
Evaluating timing and reliability reports
Performing physical verification checks
Preparing a design for tape-out readiness
Module 6: Silicon Validation and Future Semiconductor Systems
Weeks 24–27
Topics Covered:
The process from GDSII to a packaged die
Multi-project wafers, dicing, packaging, and testing
Test-board architecture and pin-map interpretation
Bring-up and debugging methods
Characterisation planning, yield, and reliability
Comparing measured and simulated performance
AI-assisted EDA, chiplets, 3D-IC, and advanced packaging
Edge AI hardware and future semiconductor systems
Skills Acquired:
Understanding the chip fabrication and packaging process
Explaining bring-up and debugging methods
Comparing measured results with specifications
Understanding yield and reliability concepts
Recognising how AI-assisted EDA and advanced packaging affect chip design
Capstone: Create One Integrated Chip From Architecture to Sign-off
The capstone is carried out parallel with the curriculum from Week 4 through Week 29. Each team chooses a reference application, such as IoT edge-sensor node, wearable sensor, or temperature sensing SoC.
The team takes a single chip design from architecture to RTL implementation, verification, analog integration, and sign-off.
Capstone Focus:
Define the chip requirements and system architecture
Develop RTL and complete the first synthesis pass
Build a verification environment and close functional coverage
Design and simulate an analog block
Complete physical implementation and sign-off checks
Document design decisions, test results, and limitations
Prepare a portfolio and defend the design at the final review
Key Deliverables:
System architecture with power, performance, and area targets
Verified RTL implementation with a UVM testbench and coverage reports
Analog front-end and comparator designs with simulation results
Physical sign-off package against the Tape-out Readiness Checklist
Design-review presentation showing individual contributions
Tools and Frameworks Covered in the IIT Kharagpur VLSI Course
Among the other VLSI Design courses this is a ai-enabled VLSI design IIT Kharagpur which cover tools such as:
1. Digital Design and Verification
Write RTL, test digital designs, and analyse verification results.
Verilog and SystemVerilog
UVM
Simulators and waveform debuggers
Python and TCL automation
Git
2. Open-Source Physical Design
Work through the chip-design flow using the SKY130 platform.
Yosys for synthesis
OpenLane for the RTL-to-GDSII flow
OpenROAD for physical design
Magic for layout work
SKY130 process platform
3. Analog and Mixed-Signal Design
Design and analyse analog circuits and their interaction with digital components.
Cadence Virtuoso
SPICE
Analog-mixed-signal co-simulation
Parasitic extraction and post-layout analysis
4. AI-Assisted EDA and Emerging Technologies
Explore tools and methods that support parts of the chip-design process.
AI-assisted verification and debugging
AI-assisted placement and timing optimisation
Commercial synthesis-to-sign-off flow, demonstrated during the programme
Chiplets and 3D-IC concepts
Who Should Enrol in IIT Kharagpur Applied VLSI Design?
Enrolling in this IIT Kharagpur VLSI course would suit you if you are:
Software & Embedded Engineers
For individuals experienced in coding, Linux, and development tools, the programme will provide an introduction to semiconductor basics, RTL Design, Verification, and Physical Design.
Early Career VLSI & RTL Engineers
For individuals working in RTL design or other digital engineering fields, the curriculum can help explore Verification, Analog & Mixed-Signal Design, and Physical Design, without retreading all the way back to the beginning.
Test, DFT, and QA Engineers
For individuals working in test or quality assurance roles, but not in the semiconductor industry, the programme can help get acquainted with chip verification via Testbenches, Assertions, UVM, and Functional Coverage.
Final-Year ECE and EE Students
The programme has identified final year Electronics & Communication Engineering and Electrical Engineering students as secondary target audience. The programme is developed mainly keeping in mind the speed and needs of professional people.
IIT Kharagpur Applied VLSI Design Course Fees Structure
The IIT Kharagpur Applied VLSI design course fees come in a single fee structure.